module y( clk， rst_n, en_in, in_data, en_out, out_y ); input clk; input rst_n; input en_in; input [15:0] in_data; output[7:0] out_y; output en_out; /* 根据输入，提取rgb565各分量*/ /* 按公式计算亮度y */ //// y=0.299r+0.587g+0.114b-128(rgb888) //// y=2.460r+2.376g+0.938b-128(rgb565) /*第一步 处理浮点系数，并分别计算2.460r，2.376g,0.938b */ /* 第二步分别计算2.460r+2.376g——0.938b，并生成输出使能 */ /* 第三步 用第二步求和结果-128，得出最终输出数据 */ endmodule

// Verilog code for extracting Y component from RGB565 color format module y ( input clk, input rst_n, input en_in, input [15:0] in_data, output reg [7:0] out_y, // Output Y component output reg en_out // Output enable ); reg [9:0] r; // Red component reg [9:0] g; // Green component reg [9:0] b; // Blue component reg [10:0] y_temp; // Temporary Y value // Extracting RGB components from input data always @(posedge clk or negedge rst_n) begin if (~rst_n) begin r <= 10'd0; g <= 10'd0; b <= 10'd0; end else begin if (en_in) begin r <= {5'b0, in_data[15:11]}; // Extracting 5 bits of Red component g <= {6'b0, in_data[10:5]}; // Extracting 6 bits of Green component b <= {5'b0, in_data[4:0]}; // Extracting 5 bits of Blue component end end end // Calculating Y component always @(posedge clk) begin if (en_in) begin y_temp <= (r * 10'd246) + (g * 10'd237) + (b * 10'd93) - 10'd128; // Calculating Y value using formula out_y <= y_temp[9:2]; // Extracting the most significant 8 bits for Y component en_out <= 1'b1; // Output enable signal end else begin en_out <= 1'b0; // Disable output when input is not enabled end end endmodule [2024-06-27 16:54:11 | AI写代码神器 | 830点数解答]