Verilog代码：数字时钟模块的详细设计与实现

[3:0]tmp_digit; reg [3:0]tmp_led; wire enable; wire enable_2; reg tmp_enable; reg tmp_enable_2; reg [2:0]tmp_seg_2; decoder_2to4 decoder1(.in(tmp_digit), .out(sel)); mux_2to1 mux1(.sel(sel[0]), .in1(seg1), .in2(seg2), .out(seg)); mux_2to1 mux2(.sel(sel[1]), .in1(seg2), .in2(seg3), .out(seg)); always @(posedge clk) begin if (tmp_reset == 1) begin tmp_second_reset <= 0; tmp_push1 <= 0; tmp_push2 <= 0; tmp_push3 <= 0; end else begin tmp_second_reset <= reset; tmp_push1 <= push1; tmp_push2 <= push2; tmp_push3 <= push3; end end always @(posedge clk) begin if (tmp_reset == 1) begin digit <= 0; end else begin if (tmp_push1 == 1) begin digit <= digit + 1; if (digit > 9) begin digit <= 0; end end end end always @(posedge clk_1khz) begin if (tmp_reset == 1) begin tmp_1sec_mux_out <= 4'b0000; tmp_1min_mux_out <= 4'b0000; tmp_1hour_mux_out <= 4'b0000; end else begin if (tmp_second_reset == 1) begin tmp_1sec_mux_out <= 4'b0000; end else begin tmp_1sec_mux_out <= tmp_1sec_mux_in; end if (tmp_push1 == 1) begin tmp_1min_mux_out <= 4'b0000; end else begin tmp_1min_mux_out <= tmp_1min_mux_in; end if (tmp_push2 == 1) begin tmp_1hour_mux_out <= 4'b0000; end else begin tmp_1hour_mux_out <= tmp_1hour_mux_in; end end end always @(posedge clk) begin if (tmp_reset == 1) begin tmp_1sec_mux_in <= 4'b0000; tmp_1min_mux_in <= 4'b0000; tmp_1hour_mux_in <= 4'b0000; end else begin if (tmp_push1 == 1) begin tmp_1sec_mux_in <= tmp_1sec_mux_in + 1; if (tmp_1sec_mux_in > 9) begin tmp_1sec_mux_in <= 0; end end if (tmp_push2 == 1) begin tmp_1min_mux_in <= tmp_1min_mux_in + 1; if (tmp_1min_mux_in > 9) begin tmp_1min_mux_in <= 0; end end if (tmp_push3 == 1) begin tmp_1hour_mux_in <= tmp_1hour_mux_in + 1; if (tmp_1hour_mux_in > 9) begin tmp_1hour_mux_in <= 0; end end end end always @(posedge clk) begin if (tmp_reset == 1) begin tmp_seg_2 <= 3'b000; tmp_enable <= 1'b0; tmp_led <= 4'b0000; end else begin if (tmp_push1 == 1) begin tmp_seg_2 <= tmp_seg_2 + 1; if (tmp_seg_2 > 4) begin tmp_seg_2 <= 0; end end if (tmp_push2 == 1) begin tmp_enable <= ~tmp_enable; end if (tmp_push3 == 1) begin tmp_led <= tmp_led + 1; if (tmp_led > 9) begin tmp_led <= 0; end end end end assign enable = tmp_enable; binary_counter_1hz counter1(.clk(clk), .reset(tmp_reset), .count(tmp_clk_1khz)); counter_24h counter2(.clk(tmp_clk_1khz), .reset(tmp_second_reset), .count(tmp_1sec_mux_out)); counter_60 counter3(.clk(tmp_clk_1khz), .reset(tmp_second_reset), .count(tmp_1min_mux_out)); counter_12 counter4(.clk(tmp_clk_1khz), .reset(tmp_second_reset), .count(tmp_1hour_mux_out)); always @(posedge clk) begin if (tmp_reset == 1) begin enable_2 <= 0; end else begin if (push2 == 1) begin enable_2 <= ~enable_2; end end end assign tmp_1sec_mux_in = enable_2 ? tmp_second_reset : tmp_1sec_mux_out; always @(posedge clk) begin if (reset == 1) begin seg1 <= 7'b1111111; // displays a "-" seg2 <= 7'b1111111; // displays a "-" seg3 <= 7'b1111111; // displays a "-" end else begin case(tmp_seg_2) 3'b000: begin seg1 <= tmp_1sec_mux_in; seg2 <= tmp_1min_mux_in; seg3 <= tmp_1hour_mux_in; end 3'b001: begin seg1 <= tmp_1min_mux_in; seg2 <= tmp_1hour_mux_in; seg3 <= tmp_1sec_mux_in; end 3'b010: begin seg1 <= tmp_1hour_mux_in; seg2 <= tmp_1sec_mux_in; seg3 <= tmp_1min_mux_in; end default: begin seg1 <= tmp_1sec_mux_in; seg2 <= tmp_1min_mux_in; seg3 <= tmp_1hour_mux_in; end endcase end end assign led = tmp_led; assign seg_2 = tmp_seg_2; assign enable_2 = tmp_enable_2; endmodule ######[AI写代码神器 | 3130点数解答 | 2024-11-15 10:14:41]