Verilog HDL实现Top - Down设计：8个LED灯闪烁计数及数码管显示控制代码解析

```verilog module LED_Blink_Counter( input clk, //时钟信号 input rst, //复位信号 input start, //启动/暂停控制信号 output reg [7:0] LEDs, //8个LED控制信号 output reg [3:0] seg1, //数码管1显示值 output reg [3:0] seg2, //数码管2显示值 output reg [3:0] seg3, //数码管3显示值 output reg [3:0] seg4 //数码管4显示值 ); reg [25:0] count1; //计数器1，10秒 reg [24:0] count2; //计数器2，15秒 reg [25:0] count3; //计数器3，5秒 reg [24:0] count4; //计数器4，5秒 reg [3:0] sec1; //LED组1工作时间 reg [3:0] sec2; //LED组2工作时间 reg [3:0] sec3; //LED组3工作时间 reg [3:0] sec4; //LED组4工作时间 reg [2:0] mode; //LED工作模式选择 reg [2:0] state; //LED组内状态 reg [25:0] count; //总计时器 reg [1:0] d1_d2_state; //LED组1状态 reg [1:0] d3_d4_state; //LED组2状态 reg [1:0] d5_d6_state; //LED组3状态 reg [1:0] d7_d8_state; //LED组4状态 always @(posedge clk or posedge rst) begin if(rst) begin LEDs <= 8'b00000000; count1 <= 26'd0; count2 <= 25'd0; count3 <= 26'd0; count4 <= 25'd0; sec1 <= 4'd0; sec2 <= 4'd0; sec3 <= 4'd0; sec4 <= 4'd0; mode <= 3'd0; state <= 3'd0; count <= 26'd0; d1_d2_state <= 2'd0; d3_d4_state <= 2'd0; d5_d6_state <= 2'd0; d7_d8_state <= 2'd0; end else begin if(count == 26'd50000000) begin count <= 26'd0; mode <= mode + 1; if(mode == 3'd4) mode <= 3'd0; end else begin count <= count + 1; end case(mode) 3'd0: begin if(start) begin if(state == 3'd0) begin d1_d2_state <= d1_d2_state + 1; if(d1_d2_state == 2'd0) begin LEDs <= 8'b00000011; end else if(d1_d2_state == 2'd1) begin LEDs <= 8'b00000000; end if(d1_d2_state == 2'd1) begin count1 <= count1 + 1; if(count1 == 26'd10000000) begin count1 <= 26'd0; sec1 <= sec1 + 1; end end if(sec1 == 4'd10) begin state <= 3'd1; end end else if(state == 3'd1) begin d3_d4_state <= d3_d4_state + 1; if(d3_d4_state == 2'd0) begin LEDs <= 8'b00001100; end else if(d3_d4_state == 2'd1) begin LEDs <= 8'b00000000; end if(d3_d4_state == 2'd1) begin count2 <= count2 + 1; if(count2 == 25'd15000000) begin count2 <= 25'd0; sec2 <= sec2 + 1; end end if(sec2 == 4'd15) begin state <= 3'd2; end end else if(state == 3'd2) begin d5_d6_state <= d5_d6_state + 1; if(d5_d6_state == 2'd0) begin LEDs <= 8'b00110000; end else if(d5_d6_state == 2'd1) begin LEDs <= 8'b00000000; end if(d5_d6_state == 2'd1) begin count3 <= count3 + 1; if(count3 == 26'd5000000) begin count3 <= 26'd0; sec3 <= sec3 + 1; end end if(sec3 == 4'd5) begin state <= 3'd3; end end else if(state == 3'd3) begin d7_d8_state <= d7_d8_state + 1; if(d7_d8_state == 2'd0) begin LEDs <= 8'b11000000; end if(sec4 == 4'd5) begin state <= 3'd0; end end end end end end end assign {seg4,seg3,seg2,seg1} = (count1 < 26'd10) ? {4'd0,sec1} : (count2 < 25'd15) ? {4'd1,sec2} : (count3 < 26'd5) ? {4'd2,sec3} : {4'd3,sec4}; endmodule ``` ######[AI写代码神器 | 3147点数解答 | 2024-07-10 21:38:32]